FPGA In-Circuit Debugging Based on Logic Analysis Core

Abstract: FPGA in-circuit debugging information based on logic analysis core is provided by excellent flowmeter and flowmeter production and quotation manufacturers. As FPGAs incorporate more and more capabilities, the need for effective debugging tools will become critical. Careful advance planning of internal visibility capabilities will allow the development team to adopt the correct debug strategy to complete their design tasks faster. I know my setup. More flowmeter manufacturers choose models and price quotations. You are welcome to inquire. The following is the article details of FPGA in-circuit debugging based on logic analysis core. As FPGAs incorporate more and more capabilities, the need for effective debugging tools will become critical. Careful advance planning of internal visibility capabilities will allow the development team to adopt the correct debug strategy to complete their design tasks faster.“I know there is a problem in my design, but I don't have the internal visibility needed to find the problem quickly.”Debugging FPGA-based systems can be frustrating due to the lack of adequate internal visibility. With larger FPGAs, which often encompass the entire system, debug visibility becomes a big issue. To gain internal visibility, design engineers must dedicate some pins as debug pins rather than actually use them in the design. What tools are available for making internal FPGA trace measurements? What other techniques can maximize internal visibility with a fixed pin count? FPGA design engineers have two methods for making internal trace measurements: 1. Route nodes to pins and test using a traditional external logic analyzer. 2. Insert a logic analyzer core into the FPGA design, and route out the trace captures saved by the internal FPGA memory via JTAG. Logic Analysis FPGA developers make important decisions early in the design process, consciously or unconsciously determining how their designs can be debugged. The most common way to gain visibility into an internal FPGA is to use a logic analyzer to route internal nodes of interest to pins probed by the analyzer. This approach provides deep memory traces where the cause of the problem and its effects can be separated by a large time interval. Logic analyzers are good at measuring asynchronous events that can escape simulation. An example is the interaction of two or more clock domains with uncorrelated frequencies. The logic analyzer provides powerful triggering, and the resulting measurements can be time-correlated to other system events. Traditional logic analyzers provide state and timing modes so data can be captured synchronously or asynchronously. In timing mode, designers can see the relationship between signal transitions. In state mode, the designer has the ability to observe the bus relative to the state clock. Status mode is especially useful when debugging data paths where bus values ​​are critical. Effective real-world measurements require careful planning in advance. The main trade-off to consider when using a traditional logic analyzer is routing the node output to a probeable pin. Traditional logic analyzers can only observe signals routed to pins. Because potential in-circuit debug issues are not yet known, design engineers can dedicate only a few pins to debug. Such a low pin count may not provide enough visibility to solve the problem at hand, delaying the completion of the project. One way to maintain internal visibility while reducing the number of pins dedicated to debugging is to insert switching multiplexers into the design (see Figure 1). For example, when an FPGA design enters the circuit, it may need to observe 128 internal nodes, which requires tracking 32 channels at a time. In this case, multiplexers can be implemented in the FPGA design to route out 32 nodes in a given time. To program the multiplexer, the design engineer can download a new configuration file and switch the signals using JTAG or routing through the control lines on the multiplexer. During the design phase, test multiplexer insertion must be carefully planned. Otherwise, the design engineer may end up not being able to access the nodes that need to be debugged at the same time. Figure 1: The insertion of the test multiplexer gives the design engineer the ability to route out a subset of the internal signals, as shown in the trace captured by the Agilent16702B. A second way to minimize the number of pins dedicated to debugging is time division multiplexing (TDM). TDM multiplexing is often used for prototyping, where multiple FPGAs are used as prototypes for a single ASIC to minimize the number of dedicated pins for debugging. This technique works best with slower internal circuits. Assume that a 50MHz design using an 8-bit bus (20ns between clock edges) requires in-circuit visibility. Use 100MHz to sample the lower 4 bits during the first 10ns and the upper 4 bits during the second 10ns. In this way, with only 4 pins, all 8 bits of debug information can be captured in each 20ns cycle. After a trace has been captured, the 8-bit trace can be reconstructed by combining successive 4-bit captures. TDM multiplexing also has some disadvantages. If traces are captured with a traditional logic analyzer, triggering becomes very complex and error-prone.

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